The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area. As the demand for even smaller electronic devices has grown recently, there has grown a need for smaller and more creative packaging techniques of semiconductor dies.
As semiconductor technologies evolve, three-dimensional integrated circuit devices have emerged as an effective alternative to further reduce the physical size of a semiconductor chip. In a three-dimensional integrated circuit, the packaging is generated on the die with contacts provided by a variety of bumps. Much higher density can be achieved by employing three-dimensional integrated circuit devices. Furthermore, three-dimensional integrated circuit devices can achieve smaller form factors, cost-effectiveness, increased performance and lower power consumption.
A three-dimensional integrated circuit device may comprise a top active circuit layer, a bottom active circuit layer and a plurality of inter-layers. In the three-dimensional integrated circuit, two semiconductor dies may be bonded together through a plurality of bumps and electrically coupled to each other through a plurality of through vias. The bumps and through vias provide an electrical interconnection in the vertical axis of the three-dimensional integrated circuit. As a result, the signal paths between two semiconductor dies are shorter than those in a traditional three-dimensional integrated circuit device in which different semiconductor dies are bonded together using interconnection technologies such as wire bonding based chip stacking packages. A three-dimensional integrated circuit device may comprise a variety of semiconductor dies stacked together. The multiple semiconductor dies are packaged before the wafer has been diced.
The three-dimensional integrated circuit technology has a variety of advantages. One advantageous feature of packaging multiple semiconductor dies at the wafer level is multi-chip wafer level package techniques may reduce fabrication costs. Another advantageous feature of wafer level package based multi-chip semiconductor devices is that parasitic losses are reduced by employing bumps and through vias.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.